Graphene for Integrated Circuit Applications - GRAPHICA

Graphene for Integrated Circuit Applications - GRAPHICA

Direct growth of high quality, large area and uniform graphene layers on arbitrary insulating substrates still remains one of a key challenges for the successful integration of graphene into the novel microelectronic devices. Therefore, developments of new approaches for the fabrication of graphene-based nanostructures with high quality graphene and tailored interfaces is of the highest importance. 

 

In the GRAPHICA project, we aimed to develop Si-technology compatible graphene synthesis method and bring the growth method to a new level of technological maturity and demonstrate its suitability for fabrication of graphene-based electronic devices in a 200 mm CMOS pilot line.

During the project the following has been achieved:

  • The influence of substrate layouts and catalyst thickness on the proof-of-concept graphene growth has been determined.
  • The influence of the wide range of the CVD processing parameters on the properties of grown layers has been investigated.
  • The pilot study and the integration of developed layouts into the CMOS platform for the fabrication of the graphene based devices has been demonstrated.
  • A technical analysis for the development of next generation CVD equipment at Aixtron for CMOS based graphene application was obtained.

Project Details

Publication date 2018/09/13
Call Topic Integrated Computational Materials Engineering (ICME) (Call 2013)
Duration in months 36
Partners
  • IHP, Germany (Coordinator)
  • AIXTRON SE, Germany (Partner)
  • ITME, Poland (Partner)
  • Nano-Carbon, Poland (Partner)
Funded by
Total project cost € 1,515,500
Contact IHP

Im Technologiepark 25, Frankfurt (Oder), Germany

Dr. Mindaugas Lukošius
Email: lukosius@ihp-microelectronics.com
Link to ERA-LEARN View on ERA-LEARN website