Graphene for Integrated Circuit Applications - GRAPHICA

Project summary

Development of new approaches for the fabrication of graphene-based nanostructures with high quality graphene and tailored interfaces is of the highest importance. In this proposal, the main objective is to develop Si-technology compatible and transfer-free graphene synthesis method. This project aims to bring the Ni-assisted growth method to a new level of technological maturity and demonstrate its suitability for fabrication of graphene-based electronic devices in a state-of-the-art 200 mm CMOS pilot line. Towards this goal, we will investigate the interdependencies between gas phase chemistry, graphene formation and reactions with the insulator surface, as well as the full spectrum of technology integration-related aspects. In addition, the optimization of the CVD graphene growth method on semi-insulating SiC will be carried out. Finally, the transfer methods for CVD graphene will be scaled up to 200 mm wafers to show their potential with standard microelectronic manufacturing.

Project Details

Call

Call 2013


Call Topic

Interfaces, Surfaces and Coatings


Project start

05.01.2015


Project end

31.07.2018


Total project costs

1.520.000 €


Total project funding

1.150.000 €


TRL

-


Coordinator

Dr. Mindaugas Lukosius

IHP, Im Technologiepark 25, 15236 Frankfurt Oder, Germany


Partners and Funders Details

Consortium Partner   Country Funder
IHP
https://www.ihp-microelectronics.com
Research org. Germany DE-JÜLICH
AIXTRON SE
https://www.aixtron.com
Large industry Germany DE-JÜLICH
ITME
http://www.itme.edu.pl/
Research org. Poland PL-NCBR
Nanocarbon ltd.
http://www.nano-carbon.pl
SME Poland PL-NCBR

Keywords

Graphene, synthesis, integration, CVD, Ni, SiC